C515C_9711 Datasheet, PDF (185/268 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515C
The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the
beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the
beginning of the machine cycle which follows the write result cycle.
The interrupt flag IADC is set at the end of the A/D conversion. If the A/D converter interrupt is
enabled and the A/D converter interrupt is priorized to be serviced immediately, the first instruction
of the interrupt service routine will be executed in the third machine cycle which follows the write
result cycle. IADC must be reset by software.
Depending on the application, typically there are three methods to handle the A/D conversion in the
C515C.
– Software delay
The machine cycles of the A/D conversion are counted and the program executes a software
delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is
the fastest method to get the result of an A/D conversion.
– Polling BSY bit
The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB instruction
which is two machine cycles long, possibly may not recognize the BSY=0 condition during the
write result cycle in the continuous conversion mode.
– A/D conversion interrupt
After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the
A/D conversion is read in the interrupt service routine. If other C515C interrupts are enabled,
the interrupt latency must be regarded. Therefore, this software method is the slowest method
to get the result of an A/D conversion.
Depending on the oscillator frequency of the C515C and the selected divider ratio of the conversion
clock prescaler the total time of an A/D conversion is calculated according figure 6-54 and
table 6-8. Figure 6-56 on the next page shows the minimum A/D conversion time in relation to the
oscillator frequency f_OSC. The minimum conversion time is 6 µs and can be achieved at f_OSC of
8 MHz.
Table 6-8
A/D Conversion Time for Dedicated System Clock Rates
f_OSC [MHz]
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
Prescaler
Ratio PS
÷4
÷4
÷4
÷4
÷8
f_ADC [MHz]
.5
1
1.5
2
1.25
Sample Time
t_S [µs]
4
2
1.33
1
1.6
Total Conversion
Time t_ADCC [µs]
24
12
8
6
9.6
Semiconductor Group
6-122
1997-11-01