MC68HC11PH8 Datasheet, PDF (66/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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08/Apr/97@13:55 [DS97 v 4.1]
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PH8.DS03/Modes+mem
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Mode
IRVNE E clock
IRV
IRVNE
IRVNE
after reset after reset after reset affects only can be written
Single chip
0
On
Off
E
Once
Expanded
0
On
Off
IRV
Once
Boot
0
On
Off
E
Unlimited
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Special test
1
On
On
IRV
Unlimited
LSBF — LSB-first enable (refer to Section 7)
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1 (set) – Data is transferred LSB first.
0 (clear) – Data is transferred MSB first.
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SPR2 — SPI clock rate select (refer to Section 7)
This bit adds a divide-by-four to the SPI clock chain.
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EXT4X — 4XLCK or EXTAL clock output select
This bit can be written once and can be read at any time.
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1 (set) – EXTALi clock output on the 4XOUT pin.
0 (clear) – 4XCLK clock output on the 4XOUT pin.
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This bit selects which clock is to be output on the 4XOUT pin, when enabled by the CLK4X bit in
CONFIG (see Section 3.3.2.1). On reset, or when BCS = 0, 4XCLK (the PLL output) is the same
as EXTALi. Refer to Section 2-6. There is a phase delay between EXTALi and 4XOUT.
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Note:
The 4XOUT pin is not available on 84-pin packaged devices.
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DISE — E clock output disable
This bit can be written once and can be read at any time.
1 (set) – No E clock output.
0 (clear) – E clock is output normally.
IRVNE allows E clock to be turned off in single chip modes. DISE has been added for expanded
modes, but can be used in every mode. Writing a zero to this bit prevents accidental E clock
turn-off in systems requiring this signal.
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MOTOROLA
3-20
OPERATING MODES AND ON-CHIP MEMORY
¬^TPG
MC68HC11PH8