MC68HC11PH8 Datasheet, PDF (257/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

PAOVF - bit in TFLG2 8-26
PAOVI - bit in TMSK2 8-26
PAREN - bit in CONFIG 4-13
PCKA[2:1] - bits in PWCLK 8-30
PCKB[3:1] - bits in PWCLK 8-30
PCLK[2:1] - bits in PWPOL 8-31
PCLK[4:3] - bits in PWPOL 8-31
PE - bit in SCCR1 5-8
PE2 - bit in S2CR1 5-16
PEDGE - bit in PACTL 8-25
PF - bit in SCSR1 5-11
PF2 - bit in S2SR1 5-16
phase-locked loop - see PLL
pinouts
CERQUAD 2-1
PLCC 2-1
TQFP 2-2
pins
4XOUT 2-6
E clock 2-5
EXTAL 2-3
IRQ 2-12
LIR 2-13
MODA/LIR 2-13
MODB/VSTBY 2-13
, OC1, special features 8-4 8-11
R/W 2-13
, RESET 2-3 10-2
VDD AD, VSS AD 2-2
VDD, VSS 2-2
VDDL, VDDR, VSSL, VSSR 2-2
VDDSYN 2-6
VPPE 2-12
VRH, VRL 2-13
VSTBY 2-13
XFC 2-6
XIRQ/VPPE 2-12
XTAL 2-3
PLL 2-6
bandwidth 2-7
block diagram 2-6
changing frequency 2-8
crystal frequency mask option 2-7
multiplication factor 2-11
PLLCR — PLL control reg. 2-9
synchronisation 2-8
SYNR — Synthesizer program reg. 2-11
VCOOUT 2-9
PLLCR — PLL control reg. 2-9
PLLCR — PLL control register 2-9
PLLON - bit in PLLCR 2-9
POR 10-1
stabilization delay 10-1
PORTA — Port A data reg. 4-2
PORTB — Port B data reg. 4-3
PORTC — Port C data reg. 4-4
PORTD — Port D data reg. 4-5
PORTE — Port E data reg. 4-6
PORTF — Port F data reg. 4-7
PORTG — Port G data reg. 4-8
MC68HC11PH8
PORTH — Port H data reg. 4-9
ports
, A (Timer) 2-14 4-2
, B (A[15:8], LCD) 2-14 4-3
, C (D[7:0]) 2-16 4-4
, D (SCI1, SPI1) 2-16 4-5
DDRA — Data direction reg. for port A 4-2
DDRB — Data direction reg. for port B 4-3
DDRC — Data direction reg. for port C 4-4
DDRD — Data direction reg. for port D 4-5
DDRF — Data direction reg. for port F 4-7
DDRG — Data direction reg. for port G 4-8
DDRH — Data direction reg. for port H 4-9
, E (A/D) 2-17 4-6
, F (A[7:0]) 2-17 4-7
, G (R/W, SCI2, SPI2, LCD) 2-17 4-8
, H (PWM, modulus timers) 2-18 4-9
PORTA — Port A data reg. 4-2
PORTB — Port B data reg. 4-3
PORTC — Port C data reg. 4-4
PORTD — Port D data reg. 4-5
PORTE — Port E data reg. 4-6
PORTF — Port F data reg. 4-7
PORTG — Port G data reg. 4-8
PORTH — Port H data reg. 4-9
signals 2-14
power-on reset - see POR
PPAR — Port pull-up assignment reg. 4-11
PPOL[4:1] - bits in PWPOL 8-31
PPROG — EEPROM programming control reg. 3-25
, PR[1:0] - bits in TMSK2 3-22 8-17
PRB - bit in T8BCR 8-39
PRC - bit in T8CCR 8-40
prebyte 11-7
prescaler, PWM 8-30
, priorities, resets and interrupts 10-11 10-12
program counter (PC) 11-4
programming
CONFIG 3-29
EEPROM 3-25
EPROM 3-24
protection
, of memory 3-21 3-30
registers 3-10
PSEL[4:0] - bits in HPRIO 10-12
PT - bit in SCCR1 5-8
PT2 - bit in S2CR1 6-10
PTCON - bit in BPROT 3-21
pull field 6-3
pull-ups 4-11
, pulse accumulator 8-1 8-23
block diagram 8-24
PACNT — Pulse accumulator count reg. 8-26
PACTL — Pulse accumulator control reg. 8-25
reset 10-9
TFLG2 — Timer interrupt flag 2 reg. 8-26
TMSK2 — Timer interrupt mask 2 reg. 8-26
pulse-width modulation - see PWM
push field 6-2
PWCLK — PWM clock prescaler and 16-bit select reg. 8-28
INDEX
TPG
MOTOROLA
ix