MC68HC11PH8 Datasheet, PDF (195/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

10.3
Reset and interrupt priority
Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced
first when simultaneous requests occur. Any maskable interrupt can be given priority over other
maskable interrupts.
The first six interrupt sources are not maskable by the I-bit in the CCR. The priority arrangement
for these sources is fixed and is as follows:
1) POR or RESET pin
2) Clock monitor reset
3) COP watchdog reset
4) XIRQ interrupt
– Illegal opcode interrupt — see Section 10.4.3 for details of handling
– Software interrupt (SWI) — see Section 10.4.4 for details of handling
The maskable interrupt sources have the following priority arrangement:
5) IRQ
6) Real-time interrupt
7) Timer input capture 1
8) Timer input capture 2
9) Timer input capture 3
10) Timer output compare 1
11) Timer output compare 2
12) Timer output compare 3
13) Timer output compare 4
14) Timer input capture 4/output compare 5
15) SPI2 transfer complete
16) SCI2/MI BUS system
17) Timer overflow
18) 8-bit modulus timers
19) Pulse accumulator overflow
20) Pulse accumulator input edge
21) Wired-OR port H
22) SPI1 transfer complete
23) SCI1 system
Any one of these maskable interrupts can be assigned the highest maskable interrupt priority by
writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority
arrangement remains the same. An interrupt that is assigned highest priority is still subject to
global masking by the I-bit in the CCR, or by any associated local bits. Interrupt vectors are not
affected by priority assignment. To avoid race conditions, HPRIO can only be written while I-bit
interrupts are inhibited.
10
MC68HC11PH8
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-11