MC68HC11PH8 Datasheet, PDF (108/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

5.8.2 S2CR1 — SCI2 control register 1
SCI2/MI control 1 (S2CR1)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0052 LOPS2 WOMS2 MIE2 M2 WAKE2 ILT2 PE2 PT2 0000 0000
The S2CR1 register provides the control bits that determine word length and select the method
used for the wake-up feature. Bit 5 has an MI BUS control function detailed below (for details of
the other bits see Section 5.6.2).
WOMS2 — Wired-OR mode for SCI pins (PG1, PG0)
5
1 (set) – TXD2 and RXD2 are open drains if operating as inputs.
0 (clear) – TXD2 and RXD2 operate normally.
MIE2 — Motorola interface bus enable 2
1 (set) – MI BUS is enabled for this subsystem.
0 (clear) – The SCI functions normally.
When MIE2 is set, the SCI2 registers, bits and pins assume the functionality required for MI BUS.
5.8.3 S2CR2 — SCI2 control register 2
SCI2/MI control 2 (S2CR2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0053 TIE2 TCIE2 RIE2 ILIE2 TE2 RE2 RWU2 SBK2 0000 0000
The S2CR2 register provides the control bits that enable or disable individual SCI functions. For
details of the bits, see Section 5.6.3.
5.8.4 S2SR1 — SCI2 status register 1
SCI2/MI status 1 (S2SR1)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2 NF2 FE2 PF2 1100 0000
The bits in S2SR1 indicate certain conditions in the SCI hardware and are automatically cleared
by special acknowledge sequences. For details of the bits, see Section 5.6.4.
MOTOROLA
5-16
SERIAL COMMUNICATIONS INTERFACE
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MC68HC11PH8