MC68HC11PH8 Datasheet, PDF (118/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

6.6.1 INIT2 — EEPROM mapping and MI BUS delay register
EEPROM mapping (INIT2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0037 EE3 EE2 EE1 EE0 STRX 0 M2DL1 M2DL0 0000 0000
This register sets the MI BUS delay time. INIT2 may be read at any time but bits 7–4 may be
written only once after reset in normal modes (bits 3, 1 and 0 may be written at any time).
EE[3:0] — EEPROM map position (Refer to Section 3.3.2.3.)
EEPROM is located at $xD00–$xFFF, where x is the hexadecimal digit represented by EE[3:0].
STRX — Stretch extended (Refer to Section 3.3.2.3)
1 (set) – All external accesses are extended by one E clock cycle.
6
0 (clear) – Only external access from $0000 to $1FFF (ROMAD set) or from
$C000 to $DFFF (ROMAD clear) are extended by one E clock cycle.
Bit 2 — Not implemented, always read zero.
M2DL1:M2DL0 — MI BUS delay select
These bits are used to set up the delay for the start of the NRZ receive for MI BUS operation as
shown (for a 20kHz bit rate) in the following table.
M2DL1
0
0
1
1
M2DL0
0
1
0
1
Delay factor Delay time⁽¹⁾
1
1.5625 µs⁽²⁾
2
3.1250 µs
3
4.6875 µs
4
6.2500 µs
(1) 20kHz bit rate requires 25µs (40kHz) time slots.
(2) 25µs ÷ 16
MOTOROLA
6-8
MOTOROLA INTERCONNECT BUS (MI BUS)
TPG
MC68HC11PH8