|
MC68HC11PH8 Datasheet, PDF (131/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit | |||
|
◁ |
7.5.4 OPT2 â System conï¬guration options register 2
System conÃg. options 2 (OPT2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0038 LIRDV CWOM STRCH IRVNE LSBF SPR2 EXT4X DISE x00x 0000
LIRDV â LIR driven (refer to Section 3)
1 (set) â Enable LIR push-pull drive.
0 (clear) â LIR not driven on MODA/LIR pin.
CWOM â Port C wired-OR mode (refer to Section 4)
1 (set) â Port C outputs are open-drain.
0 (clear) â Port C operates normally.
STRCH â Stretch external accesses (refer to Section 3)
1 (set) â Off-chip accesses are extended by one E clock cycle.
0 (clear) â Normal operation.
7
IRVNE â Internal read visibility/not E (refer to Section 3)
1 (set) â Data from internal reads is driven out of the external data bus.
0 (clear) â No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set) â E pin is driven low.
0 (clear) â E clock is driven out from the chip.
LSBF â LSB ï¬rst enable
1 (set) â SPI1 data is transferred LSB ï¬rst.
0 (clear) â SPI1 data is transferred MSB ï¬rst.
If this bit is set, data, which is usually transferred MSB ï¬rst, is transferred LSB ï¬rst. LSBF does not
affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 â SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the two bits in the
SPCR, this bit speciï¬es the SPI clock rate. Refer to Table 7-1.
MC68HC11PH8
SERIAL PERIPHERAL INTERFACE
TPG
MOTOROLA
7-9
|
▷ |