MC68HC11PH8 Datasheet, PDF (255/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

EVS — Evaluation system C-1
EXCOL - bit in EPROG 3-24
EXROW - bit in EPROG 3-24
EXT4X - bit in OPT2 3-20
EXTAL pin 2-3
F
FCME - bit in OPTION 10-5
FE - bit in SCSR1 5-11
FE2 - bit in S2SR1 5-16
FOC[1:5] - bits in CFORC 8-13
FPPUE - bit in PPAR 4-11
free-running counter 8-1
FREEZ - bit in CONFIG 3-13
G
GPPUE - bit in PPAR 4-11
GWOM - bit in SP2CR 2-17
H
H-bit in CCR 11-6
HPPUE - bit in PPAR 4-11
HPRIO — Highest priority I-bit interrupt & misc. reg. 3-11
I
I/O, on reset 10-8
, I4/05 - bit in PACTL 8-10 8-25
I4/O5F - bit in TFLG1 8-16
I4/O5I - bit in TMSK1 8-15
, I-bit in CCR 10-16 11-5
IC1F–IC3F - bits in TFLG1 8-16
IC1I–IC3I - bits in TMSK1 8-15
IDLE - bit in SCSR1 5-10
IDLE2 - bit in S2SR1 5-16
idle-line wakeup 5-4
IEH[7:0] - bits in WOIEH 4-10
ILIE - bit in SCCR2 5-9
ILIE2 - bit in S2CR2 5-16
illegal opcode trap 10-16
ILT - bit in SCCR1 5-8
ILT2 - bit in S2CR1 5-16
IMM - immediate addressing mode 11-7
IND, X/Y - indexed addressing modes 11-8
index registers (IX, IY) 11-2
INH - inherent addressing mode 11-8
INIT — RAM and I/O mapping reg. 3-14
INIT2 — EEPROM mapping and MI BUS delay reg. 6-8
initialization 3-12
input capture 8-8
instruction set 11-8
, , , internal oscillator 3-17 9-4 9-5 A-16
interrupts
8-bit modulus timers 10-25
, I-bit 10-16 11-5
illegal opcode trap 10-16
IRQ 2-12
maskable 10-17
multiple sources 2-12
non-maskable 10-16
priorities 10-11
priority resolution 10-21
, SCI 5-14 10-24
sensitivity 2-12
stacking 10-15
SWI 10-16
triggering 2-12
types 10-15
wired-OR 2-12
, X-bit 10-16 11-6
, XIRQ 2-12 10-16
IRQ pin 2-12
IRQE - bit in OPTION 3-17
IRVNE - bit in OPT2 3-19
J
junction temperature, chip A-2
L
LCD driver interface 7-1
LCD module 2-18
clock source 8-23
LCDBP - LCD backplane 2-18
LCDR — LCD control and data reg. 2-18
reset 10-10
LCD[7:4] - bits in LCDR 2-18
LCDBP - LCD backplane 2-18
LCDCK - bit in LCDR 2-19
LCDE - bit in LCDR 2-19
LCDR — LCD control and data reg. 2-18
LIR pin 2-13
LIRDV - bit in OPT2 3-18
LOOPS - bit in SCCR1 5-7
LOPS2 - bit in S2CR1 5-16
low power modes
RAM 3-5
stand-by connections 2-13
stand-by voltage 2-13
STOP 10-18
WAIT 10-17
low voltage inhibit circuit 2-3
LSBF - bit in OPT2 7-9
LVI 2-3
MC68HC11PH8
INDEX
TPG
MOTOROLA
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