MC68HC11PH8 Datasheet, PDF(102/264 Page) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HC11PH8 Datasheet, PDF (102/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

◁

5.6.4 SCSR1 â SCI status register 1

SCI1 status 1 (SCSR1)

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

$0074 TDRE TC RDRF IDLE OR NF FE PF 1100 0000

The bits in SCSR1 indicate certain conditions in the SCI hardware and are automatically cleared

by special acknowledge sequences.

TDRE â Transmit data register empty ï¬ag

1 (set) â SCDR empty.

5

0 (clear) â SCDR busy.

This ï¬ag is set when SCDR is empty. Clear the TDRE ï¬ag by reading SCSR1 with TDRE set and

then writing to SCDR.

TC â Transmit complete ï¬ag

1 (set) â Transmitter idle.

0 (clear) â Transmitter busy.

This ï¬ag is set when the transmitter is idle (no data, preamble, or break transmission in progress).

Clear the TC ï¬ag by reading SCSR1 with TC set and then writing to SCDR.

RDRF â Receive data register full ï¬ag

1 (set) â SCDR full.

0 (clear) â SCDR empty.

Once cleared, IDLE is not set again until the RXD line has been active and becomes idle again.

RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF ï¬ag by

reading SCSR1 with RDRF set and then reading SCDR.

IDLE â Idle line detected ï¬ag

1 (set) â RXD line is idle.

0 (clear) â RXD line is active.

This ï¬ag is set if the RXD line is idle. Once cleared, IDLE is not set again until the RXD line has

been active and becomes idle again. The IDLE ï¬ag is inhibited when RWU = 1. Clear IDLE by

reading SCSR1 with IDLE set and then reading SCDR.

MOTOROLA

5-10

SERIAL COMMUNICATIONS INTERFACE

TPG

MC68HC11PH8

▷