MC68HC11PH8 Datasheet, PDF (176/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

PE0/
AD0
8-bit capacitive DAC
with sample and hold
PE1/
AD1
Successive approximation
PE2/
register and control
AD2
Result
PE3/
AD3
Analog
MUX
PE4/
AD4
PE5/
AD5
PE6/
AD6
PE7/
AD7
VRH
VRL
Internal
data bus
CCF
0
SCAN
MULT
CD
CC
CB
CA
Result register interface
ADR1 - A/D result 1 ADR2 - A/D result 2 ADR3 - A/D result 3 ADR4 - A/D result 4
9
Figure 9-1 A/D converter block diagram
9.1.1 Multiplexer
The multiplexer selects one of 16 inputs for conversion. Input selection is controlled by the value
of bits CD – CA in the ADCTL register. The eight port E pins are fixed-direction analog inputs to
the multiplexer, and additional internal analog signal lines are routed to it.
Port E pins can also be used as digital inputs (see Section 4). Digital reads of port E pins should
be avoided during the sample portion of an A/D conversion cycle, when the gate signal to the
N-channel input gate is on. Because no P-channel devices are directly connected to either input
pins or reference voltage pins, voltages above V_DD do not cause a latchup problem, although
current and voltage should be limited according to maximum ratings. Refer to Figure 9-2, which is
a functional diagram of an input pin.
MOTOROLA
9-2
ANALOG-TO-DIGITAL CONVERTER
TPG
MC68HC11PH8