MC68HC11PH8 Datasheet, PDF (196/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

10.3.1 HPRIO — Highest priority I-bit interrupt and misc. register
Highest priority interrupt (HPRIO)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
RBOOT, SMOD, and MDA bits depend on power-up initialization mode and can only be written in
special modes when SMOD = 1. Refer to Table 3-4.
RBOOT — Read bootstrap ROM (refer to Section 3)
1 (set) – Bootloader ROM enabled, at $BE40–$BFFF.
0 (clear) – Bootloader ROM disabled and not in map.
SMOD — Special mode select (refer to Section 3)
1 (set) – Special mode variation in effect.
0 (clear) – Normal mode variation in effect.
MDA — Mode select A (refer to Section 3)
1 (set) – Normal expanded or special test mode in effect.
0 (clear) – Normal single chip or special bootstrap mode in effect.
PSEL[4:0] — Priority select bits
These bits select one interrupt source to be elevated above all other I-bit-related sources and can
be written to only while the I-bit in the CCR is set (interrupts disabled). See Table 10-4.
10
MOTOROLA
10-12
RESETS AND INTERRUPTS
TPG
MC68HC11PH8