MC68HC11PH8 Datasheet, PDF (43/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

2.11.5 Port E
Port E, PE/AD[7:0], is an input-only port that can also be used as the analog inputs for the
2
analog-to-digital converter.
For further information, refer to Section 4 and Section 9 (A/D).
2.11.6 Port F
Port F is an 8-bit general purpose I/O port with a data register (PORTF) and a data direction
register (DDRF). In single chip mode, port F pins are general purpose I/O pins (PF[7:0]). In
expanded mode, port F pins act as the low-order address lines (A[7:0]) of the address bus.
PORTF can be read at any time and always returns the pin level. If PORTF is written, the data is
stored in internal latches. The pins are driven only if they are configured as outputs in single chip
or bootstrap mode.
Port F pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up
assignment register (PPAR). For further information, refer to Section 4.
2.11.7 Port G
In normal modes, Port G is an 8-bit general purpose I/O port with a data register (PORTG) and a
data direction register (DDRG). Port G pin 7 is the R/W line in expanded mode; pin 6 can be used
for the LCD backplane signal (LCDBP) in any mode; the remaining pins can be used for general
purpose I/O, for one of the SCI subsystems (SCI2 with MI-bus, pins [1,0]), or for one of the serial
peripheral interface subsystems (SPI2, pins [5:2]).
PORTG can be read at any time; inputs return the pin level and outputs return the pin driver input
level. If PORTG is written, the data is stored in internal latches. The pins are driven only if they are
configured as outputs (and only in single chip or bootstrap mode for pins G[7,6]).
The GWOM bit in SP2CR disables the p-channel output drivers of pins G[5:2], and the WOMS2
bit in S2CR1 disables those of pins G[1,0]. Because the n-channel driver is not affected by GWOM
or WOMS2, setting either bit causes the corresponding port G pins to become open-drain-type
outputs suitable for wired-OR operation. In wired-OR mode (appropriate PORTG bits at logic level
zero), the pins are actively driven low by the n-channel driver. When a port G bit is at logic level
one, the associated pin is in a high impedance state as neither the n-channel nor the p-channel
devices are active. It is customary to have an external pull-up resistor on lines that are driven by
open-drain devices. Port G pins [5:0] can be configured for wired-OR operation when the MCU is
in single chip mode or expanded mode.
Port G pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up
assignment register (PPAR). For further information, refer to Section 4, Section 5 (SCI), Section 6
(MI BUS) and Section 7 (SPI).
MC68HC11PH8
PIN DESCRIPTIONS
TPG
MOTOROLA
2-17