MC68HC11PH8 Datasheet, PDF (174/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.3.2.5 T8CDR — 8-bit modulus timer C data register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
8-bit modulus timer C data (T8CDR) $005B (bit 7) (6) (5) (4) (3) (2) (1) (0) undeÞned
This 8-bit register contains the value that will be loaded into the timer C down-counter at the next
underflow. At reset, timer C is stopped and state of the modulus register is indeterminate.
8.3.2.6 T8CCR — 8-bit modulus timer C control register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
8-bit modulus timer C control (T8CCR) $005F T8CI T8CF 0
0 PRC CSC2 CSC1 CSC0 0000 0000
T8CI8 — bit timer C interrupt enable
1 (set) – Hardware interrupt requested when T8CF flag set.
0 (clear) – Interrupt disabled.
When set, an 8-bit modulus timer interrupt occurs when the timer reaches $00. At this time the
8
timer counter is loaded with the value stored in T8CDR and the 8-bit counter will continue to count
down at the selected clock rate.
T8CF — 8-bit timer C underflow flag
1 (set) – Underflow has occurred.
0 (clear) – No underflow has occurred.
Set when 8-bit modulus timer C reaches $00. An interrupt is generated if enabled by T8CI. This
bit is cleared by a write to the T8CCR register with T8CF set.
Bits [5, 4] — Not implemented; always read zero
PRC — 8-bit timer C preset
A write to the T8CCR register with this bit set will preset the timer C counter to the modulus register
value. The clock must be stopped before writing to the register. This bit always reads as 0.
CSC[2:0] — 8-bit timer C clock rate
These bits select the timer C clock, as shown in Table 8-6. At reset, timer C is not clocked.
MOTOROLA
8-40
TIMING SYSTEM
TPG
MC68HC11PH8