MC68HC11PH8 Datasheet, PDF (172/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.3.2.1 T8ADR — 8-bit modulus timer A data register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
8-bit modulus timer A data (T8ADR) $0059 (bit 7) (6) (5) (4) (3) (2) (1) (0) 1111 1111
This 8-bit register contains the value that will be loaded into the timer A down-counter on the next
underflow. At reset, the timer A clock source is the EXTALi clock divided by 8, and the modulus
register is initialized to its highest value.
Because timer A is used to clock the COP watchdog in applications using the PLL clock
generation, it is not possible to stop timer A. For the same reason, a write of values $00 or $01 to
this register will not be loaded from the modulus register to the counter.
8.3.2.2 T8ACR — 8-bit modulus timer A control register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
8-bit modulus timer A control (T8ACR) $005D T8AI T8AF 0
0
0 CSA2 CSA1 CSA0 0000 0000
T8AI — 8-bit timer A interrupt enable
8
1 (set) – Hardware interrupt requested when T8AF flag set.
0 (clear) – Interrupt disabled.
When set, an 8-bit modulus timer interrupt occurs when the timer reaches $00. At this time the
timer counter is loaded with the value stored in T8ADR and the 8-bit counter will continue to count
down at the selected clock rate.
T8AF — 8-bit timer A underflow flag
Set when 8-bit modulus timer A reaches $00. An interrupt is generated if enabled by T8AI. This bit
is cleared by a write to the T8ACR register with T8AF set.
Bits [5:3] — Not implemented; always read zero
CSA[2:0] — 8-bit timer A clock rate
These bits select the timer A clock, as shown in Table 8-6.
MOTOROLA
8-38
TIMING SYSTEM
TPG
MC68HC11PH8