MC68HC11PH8 Datasheet, PDF (64/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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08/Apr/97@13:55 [DS97 v 4.1]
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PH8.DS03/Modes+mem
CME — Clock monitor enable (refer to Section 10)
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1 (set) – Clock monitor enabled.
0 (clear) – Clock monitor disabled.
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In order to use both STOP and clock monitor, the CME bit should be set before executing STOP,
then set again after recovering from STOP.
FCME — Force clock monitor enable (refer to Section 10)
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1 (set) – Clock monitor enabled; cannot be disabled until next reset.
0 (clear) – Clock monitor follows the state of the CME bit.
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When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
STOP mode, FCME should always be cleared.
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CR[1:0] — COP timer rate select bits (refer to Section 10)
These control bits determine a scaling factor for the watchdog timer.
7 ^{3.3.2.5 OPT2 — System configuration options register 2}
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Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System conÞg. options 2 (OPT2) $0038 LIRDV CWOM STRCH IRVNE LSBF SPR2 EXT4X DISE x00x 000t0
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10
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LIRDV — LIR driven
1 (set) – Enable LIR push-pull drive.
0 (clear) – LIR not driven on MODA/LIR pin.
This bit allows power savings in expanded modes by turning off the LIR output (it has no meaning
in single chip or bootstrap modes). The LIR pin is driven low to indicate that execution of an
instruction has begun. In order to detect consecutive instructions in a high speed application, this
signal drives high for a quarter of a cycle to prevent false triggering. An external pull-up is required
in expanded modes, while a hardwired VSS connection is possible in single chip modes. LIRDV
is reset to zero in single chip modes, and to one in expanded modes.
CWOM — Port C wired-OR mode (refer to Section 4)
1 (set) – Port C outputs are open-drain.
0 (clear) – Port C operates normally.
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MOTOROLA
3-18
OPERATING MODES AND ON-CHIP MEMORY
¬^TPG
MC68HC11PH8