MC68HC11PH8 Datasheet, PDF (109/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

5.8.5 S2SR2 — SCI2 status register 2
SCI2/MI status 2 (S2SR2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0055 0
0
0
0
0
0
0 RAF2 0000 0000
In the S2SR2 only bit 0 is used, to indicate receiver active (see Section 5.6.5 for details). The other
seven bits always read zero.
5.8.6 S2DRH, S2DRL — SCI2 data high/low registers
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
5
SCI2/MI data high (S2DRH)
$0056 R8B T8B 0
0
0
0
0
0 undeÞned
SCI2/MI data low (S2DRL)
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undeÞned
S2DRH/S2DRL is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the receive data
buffer and writes access the transmit data buffer. Data received or transmitted is double buffered.
See Section 5.6.6 for more details.
MC68HC11PH8
SERIAL COMMUNICATIONS INTERFACE
TPG
MOTOROLA
5-17