MC68HC11PH8 Datasheet, PDF (179/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

9.1.7 Conversion process
The A/D conversion sequence begins one E clock cycle after a write to the A/D control/status
register, ADCTL. The bits in ADCTL select the channel and the mode of conversion.
An input voltage equal to V_RL converts to $00 and an input voltage equal to V_RH converts to $FF
(full scale), with no overflow indication. For ratiometric conversions of this type, the source of each
analog input should use V_RH as the supply voltage and be referenced to V_RL.
9.2
A/D converter power-up and clock select
ADPU (bit 7 of the OPTION register) controls A/D converter power up. Clearing ADPU removes
power from and disables the A/D converter system; setting ADPU enables the A/D converter
system. After the A/D converter is turned on, the analog bias voltages will take up to 100µs to
stabilize.
When the A/D converter system is operating from the MCU E clock, all switching and comparator
operations are synchronized to the MCU clocks. This allows the comparator results to be sampled
at ‘quiet’ times, which minimizes noise errors. The internal RC oscillator is asynchronous with
respect to the MCU clock, so noise can affect the A/D converter results. This results in a slightly
lower typical accuracy when using the internal oscillator (CSEL = 1).
9.2.1 OPTION — System configuration options register 1
9
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System conÞg. options 1 (OPTION) $0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
The 8-bit special-purpose OPTION register sets internal system configuration options during
initialization. The time protected control bits, IRQE, DLY, FCME and CR[1:0] can be written to only
once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They may be written at any time
in special modes.
ADPU — A/D power-up
1 (set) – A/D system power enabled.
0 (clear) – A/D system disabled, to reduce supply current.
After enabling the A/D power, at least 100µs should be allowed for system stabilization.
MC68HC11PH8
ANALOG-TO-DIGITAL CONVERTER
TPG
MOTOROLA
9-5