MC68HC11PH8 Datasheet, PDF (128/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7.5.1 SPCR — SPI control register
SPI control (SPCR)
Address bit 7
$0028 SPIE
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPIE — Serial peripheral interrupt enable
1 (set) – A hardware interrupt sequence is requested each time SPIF or
MODF is set.
0 (clear) – SPI interrupts are inhibited.
Set the SPIE bit to a one to request a hardware interrupt sequence each time the SPIF or MODF
status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the condition code
register is one.
SPE — Serial peripheral system enable
1 (set) – Port D [5:2] is dedicated to the SPI.
7
0 (clear) – Port D has its default I/O functions and the clock generator is stopped.
When the SPE bit is set, the port D pins 2, 3, 4, and 5 are dedicated to the SPI functions and lose
their general purpose I/O functions. When the SPI system is enabled and expects any of PD[4:2]
to be inputs then those pins will be inputs regardless of the state of the associated DDRD bits. If
any of PD[4:2] are expected to be outputs then those pins will be outputs only if the associated
DDRD bits are set. However, if the SPI is in the master mode, DDD5 determines whether PD5 is
an error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1).
DWOM — Port D wired-OR mode
1 (set) – Port D [5:2] buffers configured for open-drain outputs.
0 (clear) – Port D [5:2] buffers configured for normal CMOS outputs.
MSTR — Master mode select
1 (set) – Master mode
0 (clear) – Slave mode
CPOL — Clock polarity
1 (set) – SCK is active low.
0 (clear) – SCK is active high.
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master
device has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 7-2 and
Section 7.2.1.
MOTOROLA
7-6
SERIAL PERIPHERAL INTERFACE
TPG
MC68HC11PH8