MC68HC11PH8 Datasheet, PDF (133/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7.6.1 SP2CR — SPI2 control register
SPI2 control (SP2CR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$004C SP2IE SP2E GWOM MSTR2 CPOL2 CPHA2 SP2R1 SP2R0 0000 01uu
For details of the functions of bits 2,3,4,6 and 7, see Section 7.5.1.
GWOM — Port G wired-OR mode
1 (set) – Port G [5:2] buffers configured for open-drain outputs.
0 (clear) – Port G [5:2] buffers configured for normal CMOS outputs.
SP2R1 and SP2R0 — SPI2 clock rate selects
These two bits, along with the SP2R2 bit, select the SPI clock rate as shown in Table 7-1. Note
that SP2R2 is located in the SP2OPT register, and that its state on reset is zero.
7.6.2 SP2SR — SPI2 status register
7
SPI2 status (SP2SR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$004D SP2IF WCOL2 0 MODF2 0
0
0
0 0000 0000
For a description of bits 4,6 and 7, see Section 7.5.2.
7.6.3 SP2DR — SPI2 data register
SPI2 data (SP2DR)
Address bit 7
Bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$004E (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
For a description of this register, see Section 7.5.3.
7.6.4 SP2OPT — SPI2 control options register
SPI2 control options (SP2DR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$004F 0
0
0
0 LSBF2 SP2R2 0
0 0000 0000
For a description of bits 2 and 3, see Section 7.5.4.
MC68HC11PH8
SERIAL PERIPHERAL INTERFACE
TPG
MOTOROLA
7-11