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| MC68HC11PH8 Datasheet, PDF (213/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit | |||
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JSR, Jump to subroutine
DIRECT
Main program
PC
$9D = JSR
dd
RTN Next instruction
IND, X
Main program
PC
$AD = JSR
ff
RTN Next instruction
IND, Y
Main program
PC
$18 = PRE
$AD = JSR
ff
RTN Next instruction
EXTEND
Main program
PC
$BD = JSR
hh
ll
RTN Next instruction
RTS, Return from subroutine
Main program
PC
$39 = RTS
Stack
SPÃ2
SPÃ1
SP
RTNH
RTNL
SP
SP+1
SP+2
Stack
RTNH
RTNL
BSR, Branch to subroutine
Main program
PC
$8D = BSR
rr
RTN Next instruction
Stack
SPÃ2
SPÃ1
SP
RTNH
RTNL
SWI, Software interrupt
Main program
PC
$3F = SWI
RTN
WAI, Wait for interrupt
Main program
PC
$3E = WAI
RTN
RTI, Return from interrupt
Interrupt program
PC
$3B = RTI
SPÃ9
SPÃ8
SPÃ7
SPÃ6
SPÃ5
SPÃ4
SPÃ3
SPÃ2
SPÃ1
SP
Stack
Condition Code
Accumulator B
Accumulator A
Index register (IXH)
Index register (IXL)
Index register (IYH)
Index register (IYL)
RTNH
RTNL
SP
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
Stack
Condition Code
Accumulator B
Accumulator A
Index register (IXH)
Index register (IXL)
Index register (IYH)
Index register (IYL)
RTNH
RTNL
LEGEND
RTN Address of the next instruction in the main program, to be executed on return from subroutine
RTNH More signiÃcant byte of return address
RTNL Less signiÃcant byte of return address
Shaded cells show stack pointer position after the operation is complete
dd 8-bit direct address ($0000Ã$00FF); the high byte is assumed to be $00
ff 8-bit positive offset ($00 to $FF (0 to 256)) is added to the index register contents
hh High order byte of 16-bit extended address
ll Low order byte of 16-bit extended address
rr Signed relative offset ($80 to $7F (Ã128 to +127)); offset is relative to the address following the offset byte
11
MC68HC11PH8
Figure 11-2 Stacking operations
CPU CORE AND INSTRUCTION SET
TPG
MOTOROLA
11-3
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