MC68HC11PH8 Datasheet, PDF (221/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Table 11-2 Instruction set (Sheet 3 of 6)
Mnemonic
CPD (opr)
Operation
Compare D with memory (16-bit)
CPX (opr) Compare IX with memory (16-bit)
CPY (opr) Compare IY with memory (16-bit)
DAA
DEC (opr)
Decimal adjust A
Decrement memory byte
DECA
DECB
DES
DEX
DEY
EORA (opr)
Decrement accumulator A
Decrement accumulator B
Decrement stack pointer
Decrement index register X
Decrement index register Y
Exclusive OR A with memory
EORB (opr) Exclusive OR B with memory
FDIV
IDIV
INC (opr)
Fractional divide, 16 by 16
Integer divide, 16 by 16
Increment memory byte
INCA
INCB
INS
INX
INY
JMP (opr)
Increment accumulator A
Increment accumulator B
Increment stack pointer
Increment index register X
Increment index register Y
Jump
JSR (opr)
Jump to subroutine
LDAA (opr)
Load accumulator A
Description
D Ð (M:M+1)
IX Ð (M:M+1)
IY Ð (M:M+1)
adjust sum to BCD
MÐ1⇒M
AÐ1⇒A
BÐ1⇒B
SP Ð 1 ⇒ SP
IX Ð 1 ⇒ IX
IY Ð 1 ⇒ IY
A⊕M⇒A
B⊕M⇒A
D / IX ⇒ IX; r ⇒ D
D / IX ⇒ IX; r ⇒ D
M+1⇒M
A+1⇒A
B+1⇒B
SP + 1 ⇒ SP
IX + 1 ⇒ IX
IY + 1 ⇒ IY
see Figure 11-2
see Figure 11-2
M⇒A
Addressing
mode
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
INH
EXT
IND, X
IND, Y
A INH
B INH
INH
INH
INH
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
INH
INH
EXT
IND, X
IND, Y
A INH
B INH
INH
INH
INH
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
Opcode
1A 83
1A 93
1A B3
1A A3
CD A3
8C
9C
BC
AC
CD AC
18 8C
18 9C
18 BC
1A AC
18 AC
19
7A
6A
18 6A
4A
5A
34
09
18 09
88
98
B8
A8
18 A8
C8
D8
F8
E8
18 E8
03
02
7C
6C
18 6C
4C
5C
31
08
18 08
7E
6E
18 6E
9D
BD
AD
18 AD
86
96
B6
A6
18 A6
Instruction
Operand
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
Ñ
hh ll
ff
ff
Ñ
Ñ
Ñ
Ñ
Ñ
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
Ñ
Ñ
hh ll
ff
ff
Ñ
Ñ
Ñ
Ñ
Ñ
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
Cycles
5
6
7
7
7
4
5
6
6
7
5
6
7
7
7
2
6
6
7
2
2
3
3
4
2
3
4
4
5
2
3
4
4
5
41
41
6
6
7
2
2
3
3
4
3
3
4
5
6
6
7
2
3
4
4
5
Condition codes
SXH I NZVC
ÑÑÑÑ∆ ∆ ∆ ∆
ÑÑÑÑ∆ ∆ ∆ ∆
ÑÑÑÑ∆ ∆ ∆ ∆
ÑÑÑÑ∆ ∆ ? ∆
ÑÑÑÑ∆ ∆ ∆ Ñ
ÑÑÑÑ∆ ∆ ∆ Ñ
ÑÑÑÑ∆ ∆ ∆ Ñ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑ∆ ÑÑ
ÑÑÑÑÑ∆ ÑÑ
ÑÑÑÑ∆ ∆ 0 Ñ
ÑÑÑÑ∆ ∆ 0 Ñ
ÑÑÑÑÑ∆ ∆ ∆
ÑÑÑÑÑ∆ 0 ∆
ÑÑÑÑ∆ ∆ ∆ Ñ
ÑÑÑÑ∆ ∆ ∆ Ñ
ÑÑÑÑ∆ ∆ ∆ Ñ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑ∆ ÑÑ
ÑÑÑÑÑ∆ ÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑ∆ ∆ 0 Ñ
11
MC68HC11PH8
CPU CORE AND INSTRUCTION SET
TPG
MOTOROLA
11-11