MC68HC11PH8 Datasheet, PDF (156/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.5.3 PACTL — Pulse accumulator control register
Address bit 7
Pulse accumulator control (PACTL) $0026 0
bit 6 bit 5 bit 4 bit 3
PAEN PAMOD PEDGE 0
bit 2
bit 1
bit 0
State
on reset
I4/O5 RTR1 RTR0 0000 0000
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the
pulse accumulator and IC4/OC5 functions.
Bits [7, 3] — Not implemented; always read zero
PAEN — Pulse accumulator system enable (refer to Section 8.1.8)
1 (set) – Pulse accumulator enabled.
0 (clear) – Pulse accumulator disabled.
PAMOD — Pulse accumulator mode (refer to Section 8.1.8)
1 (set) – Gated time accumulation mode.
0 (clear) – Event counter mode.
8
PEDGE — Pulse accumulator edge control (refer to Section 8.1.8)
This bit has different meanings depending on the state of the PAMOD bit.
I4/O5 — Input capture 4/output compare 5 (refer to Section 8.1.8)
1 (set) – Input capture 4 function is enabled (no OC5).
0 (clear) – Output compare 5 function is enabled (no IC4).
RTR[1:0] — RTI interrupt rate select
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven either by CLK64 or by an ST4XCK/2¹⁵ clock rate that is compensated so it is independent
of the timer prescaler. These two control bits select an additional division factor. Refer to Table 8-2
and Table 8-3.
MOTOROLA
8-22
TIMING SYSTEM
TPG
MC68HC11PH8