MC68HC11PH8 Datasheet, PDF (32/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

2.5
Phase-locked loop (XFC, VDDSYN, 4XOUT)
2
The XFC and VDDSYN pins are the inputs for the on-chip PLL (phase-locked loop) circuitry. On reset,
all system clocks are derived from the internal EXTAL signal (EXTALi). If enabled (VDDSYN high), the
PLL uses the EXTALi frequency as a reference to generate a clock frequency that can be varied under
software control. The user may choose to use the PLL output instead of EXTALi as the source clock
for the system.
The PLL consists of a variable bandwidth loop filter, a voltage controlled oscillator (VCO), a
feedback frequency divider and a digital phase detector. PLL functions are controlled by the
PLLCR and SYNR registers. A block diagram of the PLL circuit is shown in Figure 2-6; refer also
to Figure 8-1.
XTAL EXTAL STOP
V_DDSYN
0.1 µF
&
f_REF
C_XFC
Phase PCOMP
detect
XFC
Loop Þlter
f_FB
Frequency divider
0.01 µF
VDDSYN
VCO
VCOOUT
BCS
Bus clock
select
Module clock
select
EXTALi
SYNR
EXTALi
MCS
4XOUT clock
select
Key:
External connection
EXT4X
Figure 2-6 PLL circuit
4XCLK
To clock
generation
circuitry
ST4XCK
For SCI
and timer
4XOUT
If enabled by the CLK4X bit in the CONFIG register, either the 4XCLK signal or the EXTALi signal
can be output on the 4XOUT pin, depending on the state of the EXT4X bit in the OPT2 register.
Refer to Figure 2-6, and to Section 3 for a description of the CLK4X and EXT4X bits. The signal
output on the 4XOUT pin could be used to clock another MCU.
Note: The 4XOUT pin is not available on 84-pin packaged devices.
MOTOROLA
2-6
PIN DESCRIPTIONS
TPG
MC68HC11PH8