MC68HC11PH8 Datasheet, PDF (177/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Analog
input
Input
protection
device
< 2 pF
+ 20 V
Ð 0.7 V
Diffusion and
poly coupler
≤ 4 kΩ
Note 1
20 pF
400 nA
junction
leakage
DAC
capacitance
V_RL
Note 1: The analog switch is closed only during the 12 cycle sample time
Note 2: All component values are approximate
Figure 9-2 Electrical model of an A/D input pin (in sample mode)
9.1.2 Analog converter
Conversion of an analog input selected by the multiplexer occurs in this block. It contains a
digital-to-analog capacitor (DAC) array, a comparator, and a successive approximation register
(SAR). Each conversion is a sequence of eight comparison operations, beginning with the most
significant bit (MSB). Each comparison determines the value of a bit in the SAR.
The DAC array performs two functions. It acts as a sample and hold circuit during the entire
conversion sequence, and provides comparison voltage to the comparator during each
successive comparison.
The result of each successive comparison is stored in the SAR. When a conversion sequence is
9
complete, the contents of the SAR are transferred to the appropriate result register.
A charge pump provides switching voltage to the gates of analog switches in the multiplexer.
Charge pump output must stabilize between 7 and 8 volts within up to 100 µs before the converter
can be used. The charge pump is enabled by the ADPU bit in the OPTION register.
9.1.3 Digital control
All A/D converter operations are controlled by bits in register ADCTL. In addition to selecting the
analog input to be converted, ADCTL bits indicate conversion status, and control whether single
or continuous conversions are performed. Finally, the ADCTL bits determine whether conversions
are performed on single or multiple channels.
MC68HC11PH8
ANALOG-TO-DIGITAL CONVERTER
TPG
MOTOROLA
9-3