MC68HC11PH8 Datasheet, PDF (193/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

10.2.5 Real-time interrupt (RTI)
The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The
rate control bits are cleared after reset and can be initialized by software before the real-time
interrupt (RTI) system is used.
10.2.6 Pulse accumulator
The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin
defaults to being a general-purpose input pin.
10.2.7 Computer operating properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared,
and disabled if NOCOP is set. The COP rate is set for the shortest duration timeout.
10.2.8 8-bit modulus timer system
On reset, the clock source for Timer A is set at EXTALi/8 and the associated modulus register is
initialized to $FF. Timers B and C are stopped on reset and pins PH6 and PH7 default to being
general purpose I/O pins.
10.2.9 Serial communications interface (SCI)
The reset condition of the SCI system is independent of the operating mode. At reset, the SCI
baud rate control register is initialized to $0004. All transmit and receive interrupts are masked and
both the transmitter and receiver are disabled so the port pins default to being general purpose
I/O lines. The SCI frame format is initialized to an 8-bit character size. The send break and receiver
wake-up functions are disabled. The TDRE and TC status bits in the SCI status register are both
set, indicating that there is no transmit data in either the transmit data register or the transmit serial
shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits are cleared.
10
Note:
The foregoing paragraph also applies to SCI2. The MI BUS function is disabled, since
MIE2 is cleared on reset.
MC68HC11PH8
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-9