MC68HC11PH8 Datasheet, PDF (130/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

WCOL — Write collision
1 (set) – Write collision.
0 (clear) – No write collision.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an
access of SPDR. Refer to Section 7.3.4 and Section 7.4.
MODF — Mode fault
1 (set) – Mode fault.
0 (clear) – No mode fault.
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to Section
7.3.4 and Section 7.4.
Bits [5, 3:0] — Not implemented; always read zero.
7 ^7.5.3
SPDR — SPI data register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SPI data (SPDR)
$002A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this
register initiates transmission or reception of a byte, and this only occurs in the master device. At
the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave
devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte
that caused the overrun, the first SPIF must be cleared by the time a second transfer of data from
the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
MOTOROLA
7-8
SERIAL PERIPHERAL INTERFACE
TPG
MC68HC11PH8