MC68HC11PH8 Datasheet, PDF (37/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

2.5.4.2 SYNR — Synthesizer program register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
2
Synthesizer program (SYNR) $002F SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0 0000 1011
The PLL frequency synthesizer multiplies the frequency of the input oscillator. The multiplication
factor is software programmable via a loop divider, which consists of a six-bit modulo N counter,
with a further two bit scaling factor.
The multiplication factor is given by 2(Y + 1)2^X, where 0 ≤ X ≤ 3 and 0 ≤ Y ≤ 63.
Bits in SYNR can be read at any time but can only be written if PLLON = 0.
Note:
Exceeding recommended operating frequencies can result in indeterminate MCU
operation.
SYNX[1:0]
These bits program the binary taps (divide by 1, 2, 4 and 8). Reset clears these bits.
SYNY[5:0]
These bits program the six-bit modulo N (1 to 64) counter. Reset sets these bits to %001011.
Note: The resolution of the multiplication factors decreases by a factor of two, as X increases:
X
Y Possible multipliers
0 0 Ð 63 2, 4, 6, 8, É, 128
1 0 Ð 63 4, 8, 12, 16, É, 256
2 0 Ð 63 8, 16, 24, 32, É, 512
3 0 Ð 63 16, 32, 48, 64, É, 1024
MC68HC11PH8
PIN DESCRIPTIONS
TPG
MOTOROLA
2-11