MC68HC11PH8 Datasheet, PDF (125/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

SCK cycle #
(for reference)
SCK (CPOL=0)
1
2
3
4
5
6
7
8
SCK (CPOL=1)
Sample input
Data out (CPHA=0)
Sample input
Data out (CPHA=1)
MSB 6
5
4
3
2
1 LSB
MSB 6
5
4
3
2
1
LSB
SS (to slave)
Note: this Þgure shows the LSBF=0 (default) case. If LSBF=1, data is transferred in the reverse order (LSB Þrst).
Figure 7-2 SPI transfer format
7.2.1 Clock phase and polarity controls
7
Software can select one of four combinations of serial clock phase and polarity using two bits in
the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which
selects an active high or active low clock, and has no significant effect on the transfer format. The
clock phase (CPHA) control bit selects one of two different transfer formats. The clock phase and
polarity should be identical for the master SPI device and the communicating slave device. In
some cases, the phase and polarity are changed between transfers to allow a master device to
communicate with peripheral slaves having different requirements.
When CPHA equals zero, the SS line must be deasserted and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is
low, a write collision error results.
When CPHA equals one, the SS line can remain low between successive transfers.
7.3
SPI signals
The following paragraphs contain descriptions of the four SPI signals: master in slave out (MISO),
master out slave in (MOSI), serial clock (SCK), and slave select (SS).
Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR
bit is clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All
SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in
DDRD register.
MC68HC11PH8
SERIAL PERIPHERAL INTERFACE
TPG
MOTOROLA
7-3