MC68HC11PH8 Datasheet, PDF (184/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

(1) Used for factory testing.
9.4.2 ADR1–ADR4 — A/D converter results registers
A/D result 1 (ADR1)
A/D result 2 (ADR2)
A/D result 3 (ADR3)
A/D result 4 (ADR4)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0031 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
$0032 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
$0033 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
$0034 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
These read-only registers hold an 8-bit conversion result. Writes to these registers have no effect.
Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set,
indicating a conversion sequence is complete. If conversion results are needed sooner, refer to
Figure 9-3, which shows the A/D conversion sequence diagram.
9.5
Operation in STOP and WAIT modes
If a conversion sequence is in progress when either the STOP or WAIT mode is entered, the
conversion of the current channel is suspended. When the MCU resumes normal operation, that
9
channel is resampled and the conversion sequence is resumed. As the MCU exits the WAIT mode,
the A/D circuits are stable and valid results can be obtained on the first conversion. However, in
STOP mode, all analog bias currents are disabled and it is necessary to allow a stabilization period
when leaving the STOP mode. If the STOP mode is exited with a delay (DLY = 1), there is enough
time for these circuits to stabilize before the first conversion. If the STOP mode is exited with no
delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D circuitry to stabilize to avoid invalid
results.
MOTOROLA
9-10
ANALOG-TO-DIGITAL CONVERTER
TPG
MC68HC11PH8