MC68HC11PH8 Datasheet, PDF (123/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7
SERIAL PERIPHERAL INTERFACE^†
The serial peripheral interface (SPI), an independent serial communications subsystem, allows
the MCU to communicate synchronously with peripheral devices, such as transistor-transistor
logic (TTL) shift registers, liquid crystal (LCD) display drivers, analog-to-digital converter
subsystems, and other microprocessors. The SPI is also capable of inter-processor
communication in a multiple master system. The SPI system can be configured as either a master
or a slave device, with data rates as high as one half of the E clock rate when configured as a
master and as fast as the E clock rate when configured as a slave.
The SPI shares I/O with four of port D’s pins and is enabled by SPE in the SPCR:
7
Pin
Alternate
function
PD2
MISO1
PD3
MOSI1
PD4
SCK1
PD5
SS1
7.1
Functional description
The central element in the SPI system is the block containing the shift register and the read data
buffer (see Figure 7-1). The system is single buffered in the transmit direction and double buffered
in the receive direction. This means that new data for transmission cannot be written to the shifter
until the previous transfer is complete; however, received data is transferred into a parallel read
data buffer so the shifter is free to accept a second serial character. As long as the first character
is read out of the read data buffer before the next serial character is ready to be transferred, no
overrun condition occurs. A single MCU register address is used for reading data from the read
data buffer and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write collision, and mode
fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those
functions that control the SPI system through the serial peripheral control register (SPCR).
† The MC68HC11PH8 contains two serial peripheral interfaces having similar operation. For ease
of reference, a full description of SPI1 is given first, followed by a summary of SPI2 (Section 7.6).
MC68HC11PH8
SERIAL PERIPHERAL INTERFACE
TPG
MOTOROLA
7-1