MC68HC11PH8 Datasheet, PDF (157/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.6 Computer operating properly watchdog function
There are two possible clock sources for the COP function (see Figure 8-1 and Figure 8-2). When
PLL clock generation is not used (VDDSYN low), the clocking chain for the COP function is tapped
off from the main timer divider chain (ST4XCK/2¹⁷). When the PLL clock generation is used
(VDDSYN high), the COP function is clocked by the underflow of the 8-bit modulus timer A
(CLK64/4). The CR[1:0] bits in the OPTION register and the NOCOP bit in the CONFIG register
control and configure the COP function. One additional register, COPRST, is used to arm and
clear the COP watchdog reset system. Refer to Section 10 for a more detailed discussion of the
COP function.
8.1.7 LCD module
There are three possible clock sources for the LCD module, under control of the LCDCK bit and
depending on the state of VDDSYN. When LCDCK = 0, the LCD module is clocked by the output
of 8-bit modulus timer A (CLK64). When LCDCK = 1, the LCD module is clocked by CLK64/8 if
PLL clock generation is used (VDDSYN high), and by ST4XCK/2¹⁸ if PLL clock generation is not
used (VDDSYN low). Refer to Figure 8-1, Figure 8-2 and Section 2.12.
8.1.8 Pulse accumulator
8
The MC68HC11PH8 has an 8-bit counter that can be configured to operate either as a simple
event counter, or for gated time accumulation, depending on the state of the PAMOD bit in the
PACTL register. Refer to the pulse accumulator block diagram, Figure 8-4.
In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin.
The maximum clocking rate for the external event counting mode is the E clock divided by two. In
gated time accumulation mode, a free-running ST4XCK/2⁸ signal drives the 8-bit counter, but only
while the external PAI pin is activated. Refer to Table 8-4. The pulse accumulator counter can be
read or written at any time.
Table 8-4 Pulse accumulator timing
Crystal frequency⁽¹⁾
4.0 MHz
8.0 MHz
12.0 MHz
16.0 MHz
ST4XCK/4 clock
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
Cycle time 2⁸/ST4XCK PACNT overßow
1000 ns 64 µs
16.384 ms
500 ns 32 µs
8.192 ms
333 ns 21.33 µs
5.461 ms
250 ns 16.0 µs
4.096 ms
(1) Crystal frequency values are only valid if the PLL is not active.
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-23