MC68HC11PH8 Datasheet, PDF (230/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

1.5
Control timing
(V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)
Characteristic ⁽¹⁾
Symbol
Frequency of operation
E clock period
Crystal frequency
External oscillator frequency
Processor control set-up time (t_PCSU = t_CYC/4 + 50ns)
Reset input pulse width ⁽²⁾
f_OP
t_CYC
f_XTAL
4f_OP
t_PCSU
PW_RSTL
(3)
PW_RSTL
(4)
2.0 MHz
Min. Max.
0
2.0
500 Ñ
Ñ
8.0
0
8.0
175 Ñ
16
Ñ
1
Ñ
3.0 MHz
Min. Max.
0
3.0
333 Ñ
Ñ 12.0
0 12.0
133 Ñ
16
Ñ
1
Ñ
4.0 MHz
Unit
Min. Max.
0
4.0 MHz
250 Ñ ns
Ñ 16.0 MHz
0 16.0 MHz
112 Ñ ns
16
1
Ñ
Ñ
t_CYC
Mode programming set-up time
t_MPS
2
Ñ
2
Ñ
2
Ñ t_CYC
Mode programming hold time
t_MPH
10
Ñ
10
Ñ
10
Ñ ns
Interrupt pulse width (IRQ edge sensitive mode)
PW_IRQ
t_CYC
+20
Ñ
t_CYC
+20
Ñ
t_CYC
+20
Ñ
ns
Timer pulse width
(Input capture and pulse accumulator inputs)
PW_TIM
t_CYC
+20
Ñ
t_CYC
+20
Ñ
t_CYC
+20
Ñ
ns
WAIT recovery start-up time
Clock monitor reset
t_WRS
Ñ
4
Ñ
4
Ñ
4
t_CYC
f_CMON
10
200
10
200
10
200 kHz
(1) All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
(2) Reset is recognized during the Þrst clock cycle it is held low. Internal circuitry then drives the pin low for eight clock cycles,
releases the pin and samples the pin level four cycles later to determine the source of the interrupt. (See Section 10.)
(3) To guarantee an external reset vector.
(4) This is the minimum input time; it can be pre-empted by an internal reset.
12
PA[3:0]⁽¹⁾
PA[3:0]⁽²⁾
PW_TIM
PA7^{(1), (3)}
PA7^{(2), (3)}
Notes
(1) Rising edge sensitive input.
(2) Falling edge sensitive input.
(3) Maximum pulse accumulator clocking rate is E clock frequency divided by two (E/2).
Figure A-2 Timer inputs
MOTOROLA
A-6
ELECTRICAL SPECIFICATIONS (STANDARD)
TPG
MC68HC11PH8