MC68HC11PH8 Datasheet, PDF (144/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.3.2 TIC1–TIC3 — Timer input capture registers
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer input capture 1 (TIC1) high $0010 (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) undeÞned
Timer input capture 1 (TIC1) low $0011 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
Timer input capture 2 (TIC2) high $0012 (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) undeÞned
Timer input capture 2 (TIC2) low $0013 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
Timer input capture 3 (TIC3) high $0014 (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) undeÞned
Timer input capture 3 (TIC3) low $0015 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undeÞned
When an edge has been detected and synchronized, the 16-bit free-running counter value is
transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter
value captures and timer counter incrementing occur on opposite half-cycles of the phase 2 clock
so that the count value is stable whenever a capture occurs. Input capture values can be read from
a pair of 8-bit read-only registers. A read of the high-order byte of an input capture register pair
inhibits a new capture transfer for one bus cycle. If a double-byte read instruction, such as LDD,
is used to read the captured value, coherency is assured. When a new input capture occurs
immediately after a high-order byte read, transfer is delayed for an additional cycle but the value
is not lost.
8
The TICx registers are not affected by reset.
8.1.3.3 TI4/O5 — Timer input capture 4/output compare 5 register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Capture 4/compare 5 (TI4/O5) high $001E (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) 1111 1111
Capture 4/compare 5 (TI4/O5) low $001F (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
Use TI4/O5 as either an input capture register or an output compare register, depending on the
function chosen for the PA3 pin. To enable it as an input capture pin, set the I4/O5 bit in the pulse
accumulator control register (PACTL) to logic level one. To use it as an output compare register,
set the I4/O5 bit to a logic level zero. Refer to Section 8.1.8.1.
The TI4/O5 register pair resets to ones ($FFFF).
MOTOROLA
8-10
TIMING SYSTEM
TPG
MC68HC11PH8