MC68HC11PH8 Datasheet, PDF (100/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

M — Mode (select character format)
1 (set) – Start bit, 9 data bits, 1 stop bit.
0 (clear) – Start bit, 8 data bits, 1 stop bit.
WAKE — Wake-up by address mark/idle
1 (set) – Wake-up by address mark (most significant data bit set).
0 (clear) – Wake-up by IDLE line recognition.
ILT — Idle line type
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1 (set) – Long (SCI counts ones only after stop bit).
0 (clear) – Short (SCI counts consecutive ones after start bit).
This bit determines which of two types of idle line detection method is used by the SCI receiver.
In short mode the stop bit and any bits that were ones before the stop bit will be considered as
part of that string of ones, possibly resulting in erroneous or premature detection of an idle line
condition. In long mode the SCI system does not begin counting ones until a stop bit is received.
PE — Parity enable
1 (set) – Parity enabled.
0 (clear) – Parity disabled.
PT — Parity type
1 (set) – Parity odd (an odd number of ones causes parity bit to be zero, an
even number of ones causes parity bit to be one).
0 (clear) – Parity even (an even number of ones causes parity bit to be zero, an
odd number of ones causes parity bit to be one).
MOTOROLA
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SERIAL COMMUNICATIONS INTERFACE
TPG
MC68HC11PH8