MC68HC11PH8 Datasheet, PDF (188/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

10.1.4 Clock monitor reset
The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges are
detected within this RC time delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled or disabled by the CME control bit in the OPTION register. The
presence of a timeout is determined by the RC delay, which allows the clock monitor to operate
without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs a clock to
function, it is disabled when the clocks stop. Therefore, the clock monitor system can detect clock
failures not detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout values between individual
devices. An E clock frequency below 10 kHz is detected as a clock monitor error. An E clock
frequency of 200 kHz or more prevents clock monitor errors. Using the clock monitor function
when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock monitor is
enabled. Because the STOP function causes the clocks to be halted, the clock monitor function
generates a reset sequence if it is enabled at the time the STOP mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register to zero to disable the clock
monitor. After recovery from STOP, set the CME bit to logic one to enable the clock monitor.
10.1.5 OPTION — System configuration options register 1
10
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System conÞg. options 1 (OPTION) $0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
The special-purpose OPTION register sets internal system configuration options during
initialization. The time protected control bits (IRQE, DLY, FCME and CR[1:0]) can be written to only
once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They may be written at any time
in special modes.
ADPU — A/D power-up (Refer to Section 9)
1 (set) – A/D system power enabled.
0 (clear) – A/D system disabled, to reduce supply current.
CSEL — Clock select (Refer to Section 9)
1 (set) – A/D, EPROM and EEPROM use internal RC clock (about 1.5MHz).
0 (clear) – A/D, EPROM and EEPROM use system E clock
(must be at least 1MHz).
MOTOROLA
10-4
RESETS AND INTERRUPTS
TPG
MC68HC11PH8