MC68HC11PH8 Datasheet, PDF (137/264 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8.1.1 Timer enable control
The 16-bit timer may be enabled or disabled under control of the T16EN bit in the PLL control
register.
8.1.1.1 PLLCR — PLL control register
PLL control (PLLCR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$002E PLLON BCS AUTO BWC VCOT MCS T16EN WEN 1010 1010
PLLON — PLL on (See Section 2.5.4.1)
1 (set) – Switch PLL on.
0 (clear) – Switch PLL off.
BCS — Bus clock select (See Section 2.5.4.1)
1 (set) – VCOOUT output drives the clock circuit (4XCLK).
0 (clear) – EXTALi drives the clock circuit (4XCLK).
AUTO — Automatic bandwidth control (See Section 2.5.4.1)
8
1 (set) – Automatic bandwidth control selected.
0 (clear) – Manual bandwidth control selected.
BWC — Bandwidth control (See Section 2.5.4.1)
1 (set) – High bandwidth control selected.
0 (clear) – Low bandwidth control selected.
VCOT — VCO test (Test mode only, see Section 2.5.4.1)
1 (set) – Loop filter operates as specified by AUTO and BWC.
0 (clear) – Low bandwidth mode of the PLL filter is disabled.
MCS — Module clock select (See Section 2.5.4.1)
1 (set) – 4XCLK is the source for the SCI and timer divider chain.
0 (clear) – EXTALi is the source for the SCI and timer divider chain.
MC68HC11PH8
TIMING SYSTEM
TPG
MOTOROLA
8-3