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MC68HC16Z1CPV16 Datasheet, PDF (77/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics
Freescale Semiconductor, Inc.
Table 4-2 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
BSR
BVC2
BVS2
CBA
CLR
CLRA
CLRB
CLRD
CLRE
CLRM
CLRW
CMPA
CMPB
COM
COMA
COMB
COMD
COME
COMW
Branch to Subroutine
(PK : PC) - 2 ⇒ PK : PC
Push (PC)
(SK : SP) - 2 ⇒ SK : SP
Push (CCR)
(SK : SP) - 2 ⇒ SK : SP
(PK : PC) + Offset ⇒ PK : PC
Branch if Overflow
Clear
If V = 0, branch
Mode
REL8
REL8
Branch if Overflow Set
If V = 1, branch
REL8
Compare A to B
Clear a Byte in
Memory
(A) − (B)
$00 ⇒ M
Clear A
Clear B
Clear D
Clear E
Clear AM
Clear a Word in
Memory
$00 ⇒ A
$00 ⇒ B
$0000 ⇒ D
$0000 ⇒ E
$000000000 ⇒ AM[35:0]
$0000 ⇒ M : M + 1
Compare A to Memory
(A) − (M)
Compare B to Memory
(B) − (M)
One’s Complement $FF − (M) ⇒ M, or M ⇒ M
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
One’s Complement A $FF − (A) ⇒ A, or M ⇒ A
One’s Complement B $FF − (B) ⇒ B, or B ⇒ B
One’s Complement D $FFFF − (D) ⇒ D, or D ⇒ D
One’s Complement E $FFFF − (E) ⇒ E, or E ⇒ E
One’s Complement
Word
$FFFF − M : M + 1 ⇒
M : M + 1, or (M : M + 1) ⇒
M:M+1
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
Instruction
Condition Codes
Opcode Operand Cycles S MV H EV N Z V C
36
rr
10 — — — — — — — —
B8
B9
371B
05
15
25
1705
1715
1725
1735
3705
3715
27F5
2775
27B7
2705
2715
2725
2735
48
58
68
78
1748
1758
1768
1778
2748
2758
2768
C8
D8
E8
F8
17C8
17D8
17E8
17F8
27C8
27D8
27E8
00
10
20
1700
1710
1720
1730
3700
3710
27F0
2770
2700
2710
2720
2730
rr
rr
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
—
gggg
gggg
gggg
hh ll
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
gggg
gggg
gggg
hh ll
6, 2 — — — — — — — —
6, 2 — — — — — — — —
2
—— —— ∆ ∆ ∆ ∆
4
—— —— 0 1 0 0
4
4
6
6
6
6
2
—— —— 0 1 0 0
2
—— —— 0 1 0 0
2
—— —— 0 1 0 0
2
—— —— 0 1 0 0
2
— 0 — 0 ————
6
—— —— 0 1 0 0
6
6
6
6
—— —— ∆ ∆ ∆ ∆
6
6
2
6
6
6
6
6
6
6
6
—— —— ∆ ∆ ∆ ∆
6
6
2
6
6
6
6
6
6
6
8
—— —— ∆ ∆ 0 1
8
8
8
8
8
8
2
—— —— ∆ ∆ 0 1
2
—— —— ∆ ∆ 0 1
2
—— —— ∆ ∆ 0 1
2
—— —— ∆ ∆ 0 1
8
—— —— ∆ ∆ 0 1
8
8
8
M68HC16 Z SERIES
USER’S MANUAL
CENTRAL PROCESSING UNIT
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4-17