MC68HC16Z1CPV16 Datasheet, PDF (295/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Table A-11 Low Voltage 16.78-MHz DC Characteristics (Continued)
(V_DD and V_DDSYN = 2.7 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)
Num
Characteristic
17 MC68CM16Z1/Z4 Power Dissipation¹¹
Input Capacitance^{2, 7}
18 All input-only pins
All input/output pins
Load Capacitance²
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
19 Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
Group 4 I/O Pins
Symbol Min
P_D
—
C_in
—
—
—
C_L
—
—
—
Max Unit
191 mW
10
pF
20
90
100
pF
100
100
NOTES:
1. Applies to:
Port ADA [7:0] — AN[7:0]
Port E [7:4] — SIZ[1:0], AS, DS
Port F [7:0] — IRQ[7:1], MODCLK
Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port MCCI[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, DSI/IPIPE1, PAI, PCLK, RESET, RXD, TSC
2. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK, PAI, PCLK, RXD
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, DSO/IPIPE0, PWMA, PWMB
Input/Output Pins:
Group 1: Port GP[7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1, DATA[15:0], DSI/IPIPE1
Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F[7:0] — IRQ[7:1], MODCLK
Port MCCI[7:3] — TXD, PCS[3:1], PCS0/SS, ADDR23/CS10/ECLK
Group 3: HALT, RESET
Group 4: MISO, MOSI, SCK
3. Does not apply to HALT and RESET because they are open drain pins.
Does not apply to port MCCI[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
4. Use of an active pulldown device is recommended.
5. Total operating current is the sum of the appropriate I_DD, I_DDSYN, I_SB, and I_DDA.
6. Current measured with system clock frequency of 16.78 MHz, all modules active.
7. This parameter is periodically sampled rather than 100% tested.
8. CPU16 in WAIT, all other modules inactive.
9. The RAM module will not switch into standby mode as long as V_SB does not exceed V_DD by more than 0.5 Volt.
The RAM array cannot be accessed while the module is in standby mode.
10. When V_DD is transitioning during a power up or power down sequence, and V_SB is applied, current flows between
the V_STBY and V_DD pins, which causes standby current to increase toward the maximum transient condition spec-
ification. System noise on the V_DD and V_STBY pins can contribute to this condition.
11. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can be
calculated using the expression:
P_D = Maximum V_DD (I_DD + I_DDSYN + I_SB) + Maximum V_DDA (I_DDA)
I_DD includes supply currents for all device modules powered by V_DD pins.
M68HC16 Z SERIES
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
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