MC68HC16Z1CPV16 Datasheet, PDF (112/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
If a fast or slow reference frequency is provided to the PLL from a source other than a
crystal, or an external system clock signal is applied through the EXTAL pin, the XTAL
pin must be left floating.
5.3.2 Clock Synthesizer Operation
V_DDSYN is used to power the clock circuits when the system clock is synthesized from
either a crystal or an externally supplied reference frequency. A separate power
source increases MCU noise immunity and can be used to run the clock when the
MCU is powered down. A quiet power supply must be used as the V_DDSYN source. Ad-
equate external bypass capacitors should be placed as close as possible to the
V_DDSYN pin to assure a stable operating frequency. When an external system clock
signal is applied and the PLL is disabled, V_DDSYN should be connected to the V_DD
supply.
A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To
maintain a 50% clock duty cycle, the VCO frequency (f_VCO) is either two or four times
the system clock frequency, depending on the state of the X bit in SYNCR. The clock
signal is fed back to a divider/counter. The divider controls the frequency of one input
to a phase comparator. The other phase comparator input is a reference signal, either
from the crystal oscillator or from an external source. The comparator generates a con-
trol signal proportional to the difference in phase between the two inputs. This signal
is low-pass filtered and used to correct the VCO output frequency.
Filter circuit implementation can vary, depending upon the external environment and
required clock stability. Figure 5-5 shows two recommended system clock filter net-
works. XFC pin leakage must be kept as low as possible to maintain optimum stability
and PLL performance.
NOTE
The standard filter used in normal operating environments is a single
0.1 µf capacitor, connected from the XFC pin to the V_DDSYN supply
pin. An alternate filter can be used in high-stability operating environ-
ments to reduce PLL jitter under noisy system conditions. Current
systems that are operating correctly may not require this filter. If the
PLL is not enabled (MODCLK = 0 at reset), the XFC filter is not re-
quired. Versions of the SIM that are configured for either slow or fast
reference use the same filter component values.
An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled (MODCLK = 0 at reset). The
XFC pin must be left floating in this case.
SYSTEM INTEGRATION MODULE
M68HC16 Z SERIES
5-6
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