MC68HC16Z1CPV16 Datasheet, PDF (50/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Table 3-5 M68HC16 Z-Series Signal Function (Continued)
Mnemonic
Signal Name
Function
PF[7:0]
Port F
Port F digital I/O port signals
PGP[7:0]
Port GP
GPT digital I/O port signals
PQS[7:0]
Port QS
QSM digital I/O port signals
PWMA, PWMB Pulse Width Modulation Output for PWM
QUOT
Quotient Out
Provides the quotient bit of the polynomial divider
R/W
Read/Write
Indicates the direction of data transfer on the bus
RESET
Reset
System reset
RXD
Receive Data (SCI)
Serial input to the SCI
RXDA¹
SCI A Receive Data
Serial input from SCI A
RXDB¹
SCI B Receive Data
Serial input from SCI B
SCK
Serial Clock (QSPI)
Clock output from QSPI in master mode; clock input to QSPI in
slave mode
SCK¹
Serial Clock (SPI)
Clock output from SPI in master mode; clock input to SPI in
slave mode
SIZ[1:0]
Size
Indicates the number of bytes to be transferred during a bus
cycle
SS
Slave Select (QSPI)
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
SS¹
Slave Select (SPI)
Causes serial transmission when the SPI is in slave mode;
causes mode fault in master mode
TSC
Three-State Control
Places all output drivers in a high-impedance state
TXD
SCI Transmit Data
Serial output from the SCI
TXDA¹
SCI A Transmit Data
Serial output from SCI A
TXDB¹
SCI B Transmit Data
Serial output from SCI B
XFC
External Filter Capacitor Connection for external phase-locked loop filter capacitor
NOTES:
1. MCCI signals present only in MC68HC16Z4/CK16Z4.
3.6 Internal Register Map
In Figures 3-8, 3-9, and 3-10, IMB ADDR[23:20] are represented by the letter Y. The
value represented by Y determines the base address of MCU module control regis-
ters. Y is equal to M111, where M is the logic state of the module mapping (MM) bit in
the system integration module configuration register (SIMCR). Since the CPU16 uses
only ADDR[19:0], and ADDR[23:20] follow the logic state of ADDR19 when CPU driv-
en, the CPU cannot access IMB addresses from $080000 to $F7FFFF. In order for the
MCU to function correctly, MM must be set (Y must equal $F). If M is cleared, internal
registers are mapped to base address $700000, and are inaccessible until a reset oc-
curs. The SRAM array is positioned by a base address register in the SRAM CTRL
block. Unimplemented blocks are mapped externally.
3-16
OVERVIEW
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