MC68HC16Z1CPV16 Datasheet, PDF (245/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
INTERNAL
MCU CLOCK
MODULUS
COUNTER
S
M
MSB
LSB
M
8/16-BIT SHIFT REGISTER
S
READ DATA BUFFER
SELECT
SPI CLOCK (MASTER)
CLOCK
M
CLOCK
LOGIC
S
SPI CONTROL
MSTR
SPE
SPI STATUS REGISTER
SHIFT
CONTROL
LOGIC
SPI CONTROL REGISTER
MISO
PMC0
MOSI
PMC1
SCK
PMC2
SS
PMC3
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 10-2 SPI Block Diagram
MCCI SPI BLOCK
Clock control logic allows a selection of clock polarity and a choice of two clocking pro-
tocols to accommodate most available synchronous serial peripheral devices. When
the SPI is configured as a master, software selects one of 254 different bit rates for the
serial clock.
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and re-
ceived (shifted in serially). A serial clock line synchronizes shifting and sampling of the
information on the two serial data lines. A slave-select line allows individual selection
of a slave SPI device. Slave devices which are not selected do not interfere with SPI
bus activities. On a master SPI device the slave-select line can optionally be used to
indicate a multiple-master bus contention.
M68HC16 Z SERIES
USER’S MANUAL
MULTICHANNEL COMMUNICATION INTERFACE
For More Information On This Product,
Go to: www.freescale.com
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