MC68HC16Z1CPV16 Datasheet, PDF (6/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

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Freescale Semiconductor, Inc.
TABLE OF CONTENTS
(Continued)
Title
Page
5.5.1.7
Function Codes .......................................................................5-32
5.5.1.8
Data Size Acknowledge Signals .............................................5-32
5.5.1.9
Bus Error Signal ......................................................................5-33
5.5.1.10
Halt Signal ...............................................................................5-33
5.5.1.11
Autovector Signal ....................................................................5-33
5.5.2
Dynamic Bus Sizing ........................................................................5-33
5.5.3
Operand Alignment .........................................................................5-35
5.5.4
Misaligned Operands ......................................................................5-35
5.5.5
Operand Transfer Cases .................................................................5-35
5.6 Bus Operation .........................................................................................5-36
5.6.1
Synchronization to CLKOUT ...........................................................5-36
5.6.2
Regular Bus Cycle ...........................................................................5-37
5.6.2.1
Read Cycle ..............................................................................5-37
5.6.2.2
Write Cycle ..............................................................................5-38
5.6.3
Fast Termination Cycles ..................................................................5-39
5.6.4
CPU Space Cycles ..........................................................................5-40
5.6.4.1
Breakpoint Acknowledge Cycle ...............................................5-41
5.6.4.2
LPSTOP Broadcast Cycle .......................................................5-42
5.6.5
Bus Exception Control Cycles .........................................................5-43
5.6.5.1
Bus Errors ...............................................................................5-44
5.6.5.2
Double Bus Faults ...................................................................5-45
5.6.5.3
Halt Operation .........................................................................5-45
5.6.6
External Bus Arbitration ...................................................................5-46
5.6.6.1
Show Cycles ...........................................................................5-47
5.7 Reset .......................................................................................................5-48
5.7.1
Reset Exception Processing ...........................................................5-48
5.7.2
Reset Control Logic .........................................................................5-48
5.7.3
Reset Mode Selection .....................................................................5-49
5.7.3.1
Data Bus Mode Selection ........................................................5-50
5.7.3.2
Clock Mode Selection .............................................................5-52
5.7.3.3
Breakpoint Mode Selection .....................................................5-52
5.7.4
MCU Module Pin Function During Reset ........................................5-52
5.7.5
Pin State During Reset ....................................................................5-53
5.7.5.1
Reset States of SIM Pins ........................................................5-54
5.7.5.2
Reset States of Pins Assigned to Other MCU Modules ..........5-54
5.7.6
Reset Timing ...................................................................................5-55
5.7.7
Power-On Reset ..............................................................................5-55
5.7.8
Use of the Three-State Control Pin .................................................5-56
5.7.9
Reset Processing Summary ............................................................5-57
5.7.10
Reset Status Register .....................................................................5-57
5.8 Interrupts .................................................................................................5-58
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