MC68HC16Z1CPV16 Datasheet, PDF (392/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Each chip-select pin has an associated base address register. A base address is the
lowest address in the block of addresses enabled by a chip select. CSBARBT contains
the base address for selection of a boot memory device. Bit and field definitions for
CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ. These regis-
ters may be read or written at any time.
ADDR[23:11] — Base Address
This field sets the starting address of a particular chip-select’s address space. The ad-
dress compare logic uses only the most significant bits to match an address within a
block. The value of the base address must be an integer multiple of the block size.
Base address register diagrams show how base register bits correspond to address
lines.
BLKSZ[2:0] — Block Size Field
This field determines the size of the block that is enabled by the chip-select.
Table D-12 shows bit encoding for the base address registers block size field.
Table D-12 Block Size Field Bit Encoding
BLKSZ[2:0]
000
001
010
011
100
101
110
111
Block Size
2 Kbytes
8 Kbytes
16 Kbytes
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
512 Kbytes
Address Lines Compared¹
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
NOTES:
1. ADDR[23:20] are the same logic level as ADDR19 during
normal operation.
D.2.20 Chip-Select Option Register Boot
CSORBT — Chip-Select Option Register Boot
$YFFA4A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE BYTE[1:0]
R/W[1:0]
STRB
DSACK[3:0]
SPACE[1:0]
IPL[2:0]
AVEC
RESET:
0
1
1
1
1
0
1
1
0
1
1
1
0
0
0
0
D.2.21 Chip-Select Option Registers
CSOR[0:10] — Chip-Select Option Registers
$YFFA4E–YFFA76
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE BYTE[1:0]
R/W[1:0]
STRB
DSACK[3:0]
SPACE[1:0]
IPL[2:0]
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D-18
REGISTER SUMMARY
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M68HC16 Z SERIES
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