MC68HC16Z1CPV16 Datasheet, PDF (432/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
D.7.7 MCCI Data Direction Register
MDDR — MCCI Data Direction Register
15
8
NOT USED
RESET:
7
DDR7
$YFFC0A
6
5
4
3
2
1
0
DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
0
0
0
0
0
0
0
0
MDDR determines whether pins configured for general-purpose I/O are inputs or out-
puts. MDDR affects both SPI function and I/O function. During reset, all MCCI pins are
configured as inputs. Table D-40 shows the effect of MDDR on MCCI pin function.
Table D-40 Effect of MDDR on MCCI Pin Function
MCCI Pin
MISO
Mode
Master
Slave
MDDR Bit
DDR0
Bit State
0
1
0
Pin Function
Serial data input to SPI
Disables data input
Disables data output
1
Serial data output from SPI
MOSI
Master
DDR1
0
Disables data output
1
Serial data output from SPI
Slave
0
Serial data input to SPI
1
Disables data input
SCK¹
Master
DDR2
—
Slave
—
Clock output from SPI
Clock input to SPI
SS
Master
DDR3
0
Assertion causes mode fault
1
General-purpose I/O
RXDB²
TXDB³
RXDA
TXDA³
Slave
—
—
—
—
DDR4
DDR5
DDR6
DDR7
0
SPI slave-select input
1
Disables slave-select input
0
General-purpose I/O
1
Serial data input to SCIB
0
General-purpose I/O
1
Serial data output from SCIB
0
General-purpose I/O
1
Serial data input to SCIA
0
General-purpose I/O
1
Serial data output from SCIA
NOTES:
1. SCK is automatically assigned to the SPI whenever the SPI is enabled (when the SPE
bit in the SPCR1 is set).
2. PMC4 and PMC6 function as general-purpose I/O pins when the corresponding RE bit
in the SCI control register (SCCR0A or SCCR0B) is cleared.
3. PMC5 and PMC7 function as general-purpose I/O pins when the corresponding TE bit
in the SCI control register (SCCR0A or SCCR0B) is cleared.
D-58
REGISTER SUMMARY
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