MC68HC16Z1CPV16 Datasheet, PDF (242/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
The SCI is a universal asynchronous receiver transmitter (UART) serial interface with
a standard non-return to zero (NRZ) mark/space format. It operates in either full- or
half-duplex mode. It also contains separate transmit and receive enable bits and a
double-transmit buffer. A modulus-type baud rate generator provides rates from 64
baud to 524 kbaud with a 16.78-MHz system clock. Word length of either eight or nine
bits is software selectable. Optional parity generation and detection provide either
even or odd parity check capability. Advanced error detection circuitry catches glitches
of up to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninter-
rupted until meaningful data is received.
10.2 MCCI Registers and Address Map
The MCCI address map occupies 64 bytes from address $YFFC00 to $YFFC3F. It
consists of MCCI global registers and SPI and SCI control, status, and data registers.
Writes to unimplemented register bits have no effect, and reads of unimplemented bits
always return zero.
The MM bit in the system integration module configuration register (SIMCR) defines
the most significant bit (ADDR23) of the IMB address for each module. Because
ADDR[23:20] are driven to the same bit as ADDR19, MM must be set to one. If MM is
cleared, IMB modules are inaccessible. Refer to 5.2.1 Module Mapping for more in-
formation about how the state of MM affects the system.
10.2.1 MCCI Global Registers
The MCCI module configuration register (MMCR) contains bits and fields to place the
MCCI in low-power operation, establish the privilege level required to access MCCI
registers, and establish the priority of the MCCI during interrupt arbitration. The MCCI
test register (MTEST) is used only during factory test of the MCCI. The SCI interrupt
level register (ILSCI) determines the level of interrupts requested by each SCI. Sepa-
rate fields hold the interrupt-request levels for SCIA and SCIB. The MCCI interrupt
vector register (MIVR) determines which three vectors in the exception vector table
are to be used for MCCI interrupts. The SPI and both SCI interfaces have separate
interrupt vectors adjacent to one another. The SPI interrupt level register (ILSPI) de-
termines the priority level of interrupts requested by the SPI. The MCCI port data reg-
isters (PORTMC and PORTMCP) are used to configure port MCCI for general-
purpose I/O. The MCCI pin assignment register (MPAR) determines which of the SPI
pins (with the exception of SCK) are used by the SPI, and which pins are available for
general-purpose I/O. The MCCI data direction register (MDDR) configures each pin as
an input or output.
10.2.1.1 Low-Power Stop Mode
When the STOP bit in the MMCR is set, the IMB clock signal to most of the MCCI mod-
ule is disabled. This places the module in an idle state and minimizes power consump-
tion.
10-2
MULTICHANNEL COMMUNICATION INTERFACE
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