MC68HC16Z1CPV16 Datasheet, PDF (247/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Pin Name
Master in, slave out (MISO)
Master out, slave in (MOSI)
Serial clock (SCK)
Slave select (SS)
Table 10-3 SPI Pin Functions
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Function
Provides serial data input to the SPI
Provides serial data output from the SPI
Provides serial output from the SPI
Provides serial input to the SPI
Provides clock output from the SPI
Provides clock input to the SPI
Detects bus-master mode fault
Selects the SPI for an externally-initiated serial transfer
10.3.3 SPI Operating Modes
The SPI operates in either master or slave mode. Master mode is used when the MCU
originates data transfers. Slave mode is used when an external device initiates serial
transfers to the MCU. The MSTR bit in SPCR selects master or slave operation.
10.3.3.1 Master Mode
Setting the MSTR bit in SPCR selects master mode operation. In master mode, the
SPI can initiate serial transfers but cannot respond to externally initiated transfers.
When the slave-select input of a device configured for master mode is asserted, a
mode fault occurs.
When using the SPI in master mode, include the following steps:
1. Write to the MMCR, MIVR, and ILSPI. Refer to 10.5 MCCI Initialization for
more information.
2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and
(optionally) SS. MISO is used for serial data input in master mode, and MOSI
is used for serial data output. Either or both may be necessary, depending on
the particular application. SS is used to generate a mode fault in master mode.
If this SPI is the only possible master in the system, the SS pin may be used for
general-purpose I/O.
3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK (serial
clock) and MOSI pins as outputs. Configure MISO and (optionally) SS as in-
puts.
4. Write to the SPCR to assign values for BAUD, CPHA, CPOL, SIZE, LSBF,
WOMP, and SPIE. Set the MSTR bit to select master operation. Set the SPE
bit to enable the SPI.
5. Enable the slave device.
6. Write appropriate data to the SPI data register to initiate the transfer.
When the SPI reaches the end of the transmission, it sets the SPIF flag in the SPSR.
If the SPIE bit in the SPCR is set, an interrupt request is generated when SPIF is as-
serted. After the SPSR is read with SPIF set, and then the SPDR is read or written to,
the SPIF flag is automatically cleared.
M68HC16 Z SERIES
USER’S MANUAL
MULTICHANNEL COMMUNICATION INTERFACE
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