MC68HC16Z1CPV16 Datasheet, PDF (377/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
D.1.1 Condition Code Register
CCR — Condition Code Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
MV
H
EV
N
Z
V
C
IP[2:0]
SM
PK[3:0]
The CCR contains processor status flags, the interrupt priority field, and the program
counter address extension field. The CPU16 has a special set of instructions that ma-
nipulate the CCR.
S — STOP Enable
0 = Stop CPU16 clocks when LPSTOP instruction is executed.
1 = Perform NOPs when LPSTOP instruction is executed.
MV — Accumulator M overflow flag
Set when overflow into AM35 has occurred.
H — Half Carry Flag
Set when a carry from A3 or B3 occurs during BCD addition.
EV — Accumulator M Extension Overflow Flag
EV is set when an overflow into AM31 has occurred.
N — Negative Flag
N is set under the following conditions:
• When the MSB is set in the operand of a read operation.
• When the MSB is set in the result of a logic or arithmetic operation.
Z — Zero Flag
Z is set under the following conditions:
• When all bits are zero in the operand of a read operation.
• When all bits are zero in the result of a logic or arithmetic operation.
V — Overflow Flag
Set when two’s complement overflow occurs as the result of an operation.
C — Carry Flag
Set when carry or borrow occurs during arithmetic operation. Also used during shifts
and rotates.
IP[2:0] — Interrupt Priority Field
The priority value in this field (0 to 7) is used to mask low priority interrupts.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is
given maximum positive or negative value, depending on the state of the AM sign bit
before overflow.
PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit address.
M68HC16 Z SERIES
REGISTER SUMMARY
USER’S MANUAL
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D-3
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