MC68HC16Z1CPV16 Datasheet, PDF (393/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
CSORBT and CSOR[0:10] contain parameters that support operations from external
memory devices. Bit and field definitions for CSORBT and CSOR[0:10] are the same.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode is selected.
1 = Synchronous mode is selected, and used with ECLK peripherals.
In asynchronous mode, chip-select assertion is synchronized with AS and DS.
In synchronous mode, the chip-select signal is asserted with ECLK.
BYTE[1:0] — Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin as-
signment register. This allows the usage of two external 8-bit memory devices to be
concatenated to form a 16-bit memory. Table D-13 shows upper/lower byte options.
Table D-13 BYTE Field Bit Encoding
BYTE[1:0]
00
01
10
11
Description
Disable
Lower byte
Upper byte
Both bytes
R/W[1:0]— Read/Write
This field causes a chip-select to be asserted only for a read, only for a write, or for
both read and write. Table D-14 shows the options.
Table D-14 Read/Write Field Bit Encoding
R/W[1:0]
00
01
10
11
Description
Disable
Read only
Write only
Read/Write
STRB — Address Strobe/Data Strobe
This bit controls the timing for assertion of a chip-select in asynchronous mode only.
Selecting address strobe causes the chip-select to be asserted synchronized with ad-
dress strobe. Selecting data strobe causes the chip-select to be asserted synchro-
nized with data strobe. Data strobe timing is used to create a write strobe when
needed.
0 = Address strobe
1 = Data strobe
DSACK[3:0] — Data Strobe Acknowledge
This field specifies the source of DSACK in asynchronous mode as internally generat-
ed or externally supplied. It also allows the user to adjust bus timing with internal
DSACK generation by controlling the number of wait states that are inserted to opti-
mize bus speed in a particular application. Table D-15 shows the DSACK[3:0] field en-
coding. The fast termination encoding (%1110) effectively corresponds to –1 wait
states.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
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D-19