MC68HC16Z1CPV16 Datasheet, PDF (142/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Table 5-16 Operand Alignment
Current
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
Transfer Case
Byte to 8-bit port (even)
Byte to 8-bit port (odd)
Byte to 16-bit port (even)
Byte to 16-bit port (odd)
Word to 8-bit port
(aligned)
Word to 8-bit port
(misaligned)
Word to 16-bit port
(aligned)
Word to 16-bit port
(misaligned)
Long word to 8-bit port
(aligned)
Long word to 8-bit port
(misaligned)²
Long word to 16-bit port
(aligned)
Long word to 16-bit port
(misaligned)²
Three byte to 8-bit port³
SIZ1
0
0
0
0
1
1
1
1
0
1
0
1
1
SIZ0
1
1
1
1
0
0
0
0
0
0
0
0
1
ADDR0 DSACK1 DSACK0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
1
1
0
DATA
[15:8]
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
DATA
[7:0]
(OP0)¹
(OP0)
(OP0)
OP0
(OP1)
(OP0)
OP1
OP0
(OP1)
(OP0)
OP1
OP0
(OP0)
NOTES:
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. The CPU16 treats misaligned long-word transfers as two misaligned-word transfers.
3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer.
Next
Cycle
—
—
—
—
2
1
—
3
13
1
7
3
5
5.6 Bus Operation
Internal microcontroller modules are typically accessed in two system clock cycles.
Regular external bus cycles use handshaking between the MCU and external periph-
erals to manage transfer size and data. These accesses take three system clock cy-
cles, with no wait states. During regular cycles, wait states can be inserted as needed
by bus control logic. Refer to 5.6.2 Regular Bus Cycle for more information.
Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Refer to 5.6.3 Fast
Termination Cycles and 5.9 Chip-Selects for more information. Bus control signal
timing, as well as chip-select signal timing, are specified in APPENDIX A ELECTRI-
CAL CHARACTERISTICS. Refer to the SIM Reference Manual (SIMRM/AD) for more
information about each type of bus cycle.
5.6.1 Synchronization to CLKOUT
External devices connected to the MCU bus can operate at a clock frequency different
from the frequencies of the MCU as long as the external devices satisfy the interface
signal timing constraints. Although bus cycles are classified as asynchronous, they are
interpreted relative to the MCU system clock output (CLKOUT).
5-36
SYSTEM INTEGRATION MODULE
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