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MC68HC16Z1CPV16 Datasheet, PDF (329/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics | |||
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Freescale Semiconductor, Inc.
Table A-27 Low Voltage QSPI Timing
(VDD and VDDSYN = 2.7 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)1
Num
Function
Operating Frequency
1 Master
Slave
Cycle Time
2 Master
Slave
Enable Lead Time
3 Master
Slave
Symbol
Min
fop
DC
DC
tqcyc
4
4
tlead
2
2
Max
1/4
1/4
510
â
128
â
Enable Lag Time
4 Master
Slave
Clock (SCK) High or Low Time
5 Master
Slave2
Sequential Transfer Delay
6 Master
Slave (Does Not Require Deselect)
Data Setup Time (Inputs)
7 Master
Slave
tlag
â
1/2
2
â
tsw
2 tcyc â 60 255 tcyc
2 tcyc â n
â
ttd
17
8192
13
â
tsu
20
â
20
â
Data Hold Time (Inputs)
8 Master
Slave
9 Slave Access Time
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
11 Master
Slave
thi
30
â
20
â
ta
â
1
tdis
â
2
tv
â
50
â
50
Data Hold Time (Outputs)
12 Master
Slave
Rise Time
13 Input
Output
Fall Time
14 Input
Output
NOTES:
1. Refer to notes in Table A-28.
tho
0
â
0
â
tri
â
2
tro
â
30
tfi
â
2
tfo
â
30
Unit
fsys
fsys
tcyc
tcyc
tcyc
tcyc
SCK
tcyc
ns
ns
tcyc
tcyc
ns
ns
ns
ns
tcyc
tcyc
ns
ns
ns
ns
µs
ns
µs
ns
M68HC16 Z SERIES
USERâS MANUAL
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
A-45
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